VHDL IMPLEMENTATION OF ADVANCED ENCRYPTION STANDARD ALGORITHM

ABSTRACT

The Data Encryption Standard (DES) is a block cipher that uses shared secret encryption. It was selected by the National Bureau of Standards as an official Federal Information Processing Standard (FIPS) for the United States in 1976 and which has subsequently enjoyed widespread use internationally. It is based on a symmetric-key algorithm that uses a 56-bit key. The algorithm was initially controversial with classified design elements, a relatively short key length, and suspicions about a National Security Agency (NSA) backdoor. In recent years, the cipher has been superseded by the Advanced Encryption Standard (AES).

The Advanced Encryption Standard can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker, more customizable solution. This research investigates the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Xilinx software is used for simulation and optimization of the synthesizable VHDL code. All the transformations of Encryption are simulated using an iterative design approach in order to minimize the hardware consumption.